Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps
US9824921B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.