Transistor with MIS connections and fabricating process

US9831319B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Julien BORREL · Le Versoud, FR
• Louis HUTIN · Grenoble, FR
• Yves Morand · Grenoble, FR
• Fabrice Nemouchi · Moirans, FR
• Heimanu Niebojewski · Grenoble, FR

Key dates

• Filing date: Mar 2, 2016
• Grant date: Nov 28, 2017
• Expiry date: Mar 2, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.