Semiconductor layout generation
US9836570B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jun 6, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.