Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US9837303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2013 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jun 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.