Forming deep airgaps without flop over
US9837305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jul 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure that includes: a semiconductor substrate having a semiconductor base and back end of the line (BEOL) wiring layers; a dielectric cap layer on the semiconductor base; trenches on the dielectric cap layer, each of the trenches including dielectric walls, a dielectric bottom in contact with the dielectric cap layer and a metal filling a space between the dielectric walls; air gap openings on the dielectric cap layer and interspersed with the trenches, each air gap opening between the dielectric wall from one metal trench and adjacent to the dielectric wall of a second metal, the dielectric cap layer forming a bottom of the air gap openings; and a second dielectric cap layer formed over the trenches and over the air gap openings, the second dielectric cap layer pinching off each air gap opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.