Semiconductor memory device, chip ID generation method thereof and manufacturing method thereof
US9852791B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2017 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Apr 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3278
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.