Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures

US9852954B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Vara Govindeswara Reddy Vakada · Beacon, US
• Laegu Kang · Hopewell Junction, US
• Michael Ganz · Fishkill, US
• Yi Qi · Niskayuna, US
• Puneet Khanna · Beacon, US
• Srikanth B. Samavedam · Austin, US
• Sri Charan Vemula · Clifton Park, US
• Manfred Eller · Wappingers Falls, US

Key dates

• Filing date: Oct 14, 2015
• Grant date: Dec 26, 2017
• Expiry date: Dec 14, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/859

Abstract

One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.