Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit
US9852986B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Nov 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon. An array of mandrels is patterned into the mandrel layer. Mandrel spacers are formed self-aligned on sidewalls of the mandrels. A gapfill layer is disposed and planarized over the semiconductor structure. Non-mandrel pillars are formed over the planarized gapfill layer. Exposed portions of the gapfill layer are etched to form non-mandrel plugs preserved by the pillars. The pillars are removed to form a pattern, the pattern including the non-mandrel plugs. The pattern is utilized to form an array of alternating mandrel and non-mandrel metal interconnection lines in the dielectric stack. The array includes non-mandrel dielectric structures formed from the non-mandrel plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.