Vertical FET with reduced parasitic capacitance

US9853028B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Xin Miao · Guilderland, US
• Philip J. Oldiges · Lagrangeville, US
• Wenyu Xu · Albany, US
• Chen Zhang · Guilderland, US

Key dates

• Filing date: Apr 17, 2017
• Grant date: Dec 26, 2017
• Expiry date: Apr 17, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.