Split-gate flash cell formed on recessed substrate

US9853039B1 · kind B1 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Sung-Taeg Kang · Austin, US
• James Pak · Sunnyvale, US
• Unsoon Kim · San Jose, US
• Inkuk Kang · San Jose, US
• Chun Chen · San Jose, US
• Kuo-Tung Chang · Saratoga, US

Key dates

• Filing date: Mar 29, 2017
• Grant date: Dec 26, 2017
• Expiry date: Mar 29, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/696

Abstract

A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.