Patent · US Active

Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers

US9853124B2 · kind B2 · utility

2Cited by

1References

14Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Sylvain Barraud · Grenoble, FR
Emmanuel Augendre · Montbonnot-Saint-Martin, FR
Sylvain Maitrejean · Paris, FR
Nicolas Posseme · Grenoble, FR

Key dates

Filing date	Nov 15, 2016
Grant date	Dec 26, 2017
Priority date	—
Expiry date	Nov 15, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/121
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Method of making a transistor with semiconducting nanowires, including:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.