Methods and structures to repair device warpage
US9859234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2015 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Aug 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.