Memory system with timing overlap mode for activate and precharge operations
US9870812B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Dec 6, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Dec 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.