Vertical transistor devices for embedded memory and logic technologies
US9871117B2 · kind B2 · utility
2Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.