Vertical memory cell with non-self-aligned floating drain-source implant
US9876122B2 · kind B2 · utility
2Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Nov 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.