Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof
US9881929B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2016 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Oct 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings, filled with first support pillar structures and sacrificial pillar structures, respectively, are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed thereabove. Second support openings and second memory openings are formed through the second tier structure such that the second support openings do not overlap with the first support pillar structures and the second memory openings overlie the sacrificial pillar structures. Inter-tier memory openings are formed by removal of the sacrificial pillar structures. Memory stack structures and second support pillar structures are formed in the inter-tier memory openings and the second support openings, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.