Method of making split gate non-volatile memory cell with 3D FinFET structure

US9887206B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Chien-Sheng Su · Saratoga, US
• Jeng-Wei Yang · Zhubei City, TW
• Man-Tang Wu · Hengshan, TW
• Chun-Ming Chen · Boise, US
• Hieu Van Tran · San Jose, US
• Nhan Do · Saratoga, US

Key dates

• Filing date: Mar 8, 2017
• Grant date: Feb 6, 2018
• Expiry date: Mar 8, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.