Error detection circuitry for use with memory
US9891976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Feb 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.