Cache memory budgeted by chunks based on memory access type
US9898411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2014 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Feb 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways, each set belongs in one of L mutually exclusive groups; an allocation unit allocates the storage elements in response to memory accesses that miss in the cache; each memory access has an associated memory access type (MAT) of a plurality of predetermined MAT; a mapping, for each group of the L mutually exclusive groups: for each MAT, associates the MAT with a subset of the N ways; and for each memory access, the allocation unit allocates into a way of the subset of ways that the mapping associates with the MAT of the memory access and with one of the L mutually exclusive groups in which the selected set belongs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.