Area efficient parallel test data path for embedded memories
US9899103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2017 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Feb 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.