Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain
US9899515B1 · kind B1 · utility
34Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Oct 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.