Computer-based square root and division operations
US9910638B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2016 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Aug 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.