Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure
US9911592B2 · kind B2 · utility
10Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2016 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Sep 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.