Method for fabrication of a field-effect with reduced stray capacitance
US9911820B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Mar 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.