Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
US9917100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2016 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Nov 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.