Three-dimensional memory device containing separately formed drain select transistors and method of making thereof
US9922987B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2017 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory stack structures can be formed through an alternating stack of insulating layers and spacer material layers that are formed as, or are subsequently replaced with, electrically conductive layers. The memory stack structures can be formed as rows having a first pitch. Additional insulating layers and at least one drain select level dielectric layer are formed over the alternating stack. Drain select level openings are formed in rows having a smaller second pitch. Partial replacement of the at least one drain select level dielectric layer forms spaced apart electrically conductive line structures that surround a respective plurality of drain select level openings. Drain select level channel portions are subsequently formed in respective drain select level openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.