Semiconductor memory device and method for manufacturing same
US9922991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Sep 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.