Gate height control and ILD protection
US9923080B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2017 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Feb 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.