Stress mitigation for thin and thick films used in semiconductor circuitry
US9934983B2 · kind B2 · utility
3Cited by
7References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2014 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | May 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.