Method of fabricating a transistor channel structure with uniaxial strain
US9935019B2 · kind B2 · utility
2Cited by
1References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 9, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Sep 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for creation of stressed channel structure transistors wherein at least one amorphizing ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.