Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof
US9935050B2 · kind B2 · utility
24Cited by
37References
20Claims
0Family size
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Key dates
| Filing date | Jun 27, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Jun 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.