Reducing metallic interconnect resistivity through application of mechanical strain

US9941211B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Benjamin D. Briggs · Cohoes, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Nicholas Anthony Lanzillo · Wynantskill, US
• Michael Rizzolo · Delmar, US
• Theodorus E. Standaert · Clifton Park, US

Key dates

• Filing date: Mar 24, 2017
• Grant date: Apr 10, 2018
• Expiry date: Mar 24, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76883
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.