Method of forming vertical transistor having dual bottom spacers
US9941391B2 · kind B2 · utility
8Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Aug 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.