Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
US9947804B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Jul 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An IC structure according to the disclosure includes: a substrate; a pair of transistor sites positioned on the substrate, wherein an upper surface of the substrate laterally between the pair of transistor sites defines a separation region; a pair of nanosheet stacks, each positioned on one of the pair of transistor sites; an insulative liner conformally positioned on the upper surface of the substrate within the separation region, and a sidewall surface of each of the pair of transistor sites; a semiconductor mandrel positioned on the insulative liner and over the separation region; a pair of insulator regions each positioned laterally between the semiconductor mandrel and the insulative liner on the sidewall surfaces of each of the pair of transistor sites; and a source/drain epitaxial region positioned over the pair of insulator regions and the semiconductor mandrel, wherein the source/drain epitaxial region laterally abuts the pair of nanosheet stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.