NAND structure with tier select gate transistors
US9953717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.