Bottom spacer formation for vertical transistor

US9954103B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Oleg Gluschenkov · Poughkeepsie, US
• Sanjay C. Mehta · Niskayuna, US
• Shogo Mochizuki · Clifton Park, US
• Alexander Reznicek · Troy, US

Key dates

• Filing date: Sep 25, 2017
• Grant date: Apr 24, 2018
• Expiry date: Sep 25, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.