Patent · US Active

Binary fused multiply-add floating-point calculations

US9959093B2 · kind B2 · utility

1Cited by

10References

14Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Klein · Schenefeld, DE
Klaus M. Kroener · Ehningen, DE
Cedric Lichtenau · Stuttgart, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Jun 29, 2016
Grant date	May 1, 2018
Priority date	—
Expiry date	Jun 29, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2207/483
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.