Patent · US Active

Single cycle instruction pipeline scheduling

US9959122B2 · kind B2 · utility

0Cited by
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20Claims
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Assignee

Inventors

Key dates

Filing dateApr 24, 2013
Grant dateMay 1, 2018
Priority date
Expiry dateSep 12, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F9/3889
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to all older single-cycle instructions allocated to the first pipeline being ready and eligible to be picked for execution. An apparatus includes a decoder to decode a first single-cycle instruction and to allocate the first single-cycle instruction to a first pipeline. The apparatus further includes a scheduler to pick single-cycle instructions for execution by the first pipeline in program order and to mark at least one source register of the first single-cycle instruction as ready for execution in the first pipeline in response to determining that all older single-cycle instructions allocated to the first pipeline are ready and eligible.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.