Reflow interconnect using Ru
US9960078B1 · kind B1 · utility
3Cited by
19References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.