Method of forming semiconductor structure with aligning mark in dicing region
US9960123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Apr 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. Next, an aligning mark is formed in the dicing region, wherein the aligning mark is a mirror symmetrical pattern and comprises a plurality of second patterns in the middle region and a plurality of third patterns in the third region, each third pattern has a plurality of lines and the lines comprises a plurality of inner lines which are formed by a sidewall image transfer (SIT) process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.