Fully aligned via with integrated air gaps

US9966337B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Benjamin D. Briggs · Cohoes, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Huai Huang · Clifton Park, US
• Christopher J. Penny · Saratoga Springs, US
• Michael Rizzolo · Delmar, US
• Hosadurga Shobha · Armonk, US

Key dates

• Filing date: Mar 15, 2017
• Grant date: May 8, 2018
• Expiry date: Mar 15, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76883
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A wafer is provided. The wafer includes a dielectric layer, first and second metallization layer interconnects arrayed across the dielectric layer with the second metallization layer interconnects adjacent one another and surrounded by the first metallization layer interconnects and a cap. The first and second metallization layer interconnects have respective upper surfaces defining a first plane and a second plane recessed from the first plane, respectively. The cap is disposed on exposed surfaces of the second metallization layer interconnects and portions of the dielectric layer adjacent to the second metallization layer interconnects.