Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof

US9966466B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stefan Flachowsky · Dresden, DE
• Ralf Illgen · Dresden, DE

Key dates

• Filing date: Aug 8, 2016
• Grant date: May 8, 2018
• Expiry date: Aug 8, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/033
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.