Method and structure to control channel length in vertical FET device
US9972494B1 · kind B1 · utility
31Cited by
0References
15Claims
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Key dates
| Filing date | Nov 15, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Nov 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.