Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof
US9972554B2 · kind B2 · utility
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1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.