Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof
US9972640B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Nov 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.