Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US9978116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2017 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | May 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/955
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.