Techniques for reducing read disturb in partially written blocks of non-volatile memory
US9978456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2014 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Nov 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.