Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping
US9978655B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2016 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Sep 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating material disposed around a plurality of semiconductor die can be formed. An actual position for each of the plurality of semiconductor die within the panel can be measured. A conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die can be formed. A plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages can be formed. A nominal footprint of a plurality of conductive vias can be adjusted to account for a misalignment between each semiconductor die and its corresponding package outline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.