Uniform dielectric recess depth during fin reveal
US9984916B2 · kind B2 · utility
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12References
7Claims
0Family size
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Key dates
| Filing date | Jan 6, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.