Methods of forming an isolated nano-sheet transistor device and the resulting device
US9984936B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Jul 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method includes forming a sacrificial gate and a stack of materials above a semiconductor substrate, forming a trench in each of the source/drain areas of the device, wherein each trench extends into the semiconductor substrate, forming an empty space under the sacrificial gate structure, the empty space being vertically positioned between the stack of materials and the semiconductor substrate, wherein the empty space is in communication with the trenches, performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least the sacrificial gate while at least partially filling the empty space and substantially filling the trenches, and performing a recess etching process to remove at least portions of the conformal layer positioned adjacent the sacrificial gate, thereby defining a recessed upper surface of the device isolation material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.